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VL`3@*> +@m'@*@SA[B{Ǩ_֮_{ ;7?CGKOB@@9?kT*@0#'_+[DE`- @{ʨ_{ *sš$qlT\@h#8cdsQ1T?39 @{Ĩ_{ `@94s @{¨_{Sc#w9@4@?3@S[@94qT R_8QXqhTZ`xb@ AR?qLT47!?*`"3kT!?9}u@ 7!/*`"3kT!/9}u*RARb7 ?*u"3kT ?}`@7 ?*u"3kT ?}s@sRt*A?qLT47 ?*a"3?kT ?}`@ 7 /*a"3?kT /}`@*R!!?qLT47 ?*a"3?kT ?}`@ 7 /*a"3?kT /}`@*AR2gZdSA[BcC#@{Ũ_$qARTqAR@R!@!QXa_Th#8c_ҟ Thd8%_8k T`KR_T$hc8h#8c_{Sҡw#'_+[Ң{DE9js8*4*s1!TSA{Ҩ_{ *S k`Z @{¨_"@9b4! _"@_ T"@C#@9 @ _{?[SKcK@XksO@@@@K@R@Qq@R 0;K@tK @8q@Te4O@`?9@5*RRRRR RRRR R R R^RK@9 Q]q(T;@BXkxcb"@-RK@K2R RR57.6} !#?kT.*v}9*@A6@KR7.* #9kT.}G@*h5R RkK@kQ@9Q&qTK@BKh5 * *(R*6 #9kT.6}Z@*G7>*  ?kT>6}@G@h9@9!Sh`89jt8K*`4O@{`?֤{@94*R;RRR@94QG@`#|@T?kO@`?9@9qMTO@`?9!R@9qT*4O@R`?R9*69# ?kT.6}@O@`?֤@@9 7>* #9kT>}T@7>*  ?kT>}@?kR|!:Qa4@9D h`8O@`?9`@9 @ h`8O@`?9{ 4@94O@G`?֦G@9{*4 R.R)R0R4,R R*R*5l5J546 9kT>6}A@|@&#46 #9kT>6}A@$y46 #9kT>6}A@$9 6 #9kT>6}A@$*?k*6 #9kTh<}*I@ RRR,RR5*@ Rm*69# ?kT> v}@zzZs(5k{ *{@k@ k*TH_8H57KkT@*@5Q1T3O@*k{`?֧{@k@9 **T@kf8O@7?`?֦?@7@9k{ T@* 4ZQ_1 TO@*`?9{ 1R8* R\R *+R /R/* RR* RR55q5J5o46 #9kT>6}I@ i46 #9kT.6}I@yn46 #9kT.6}I@9 6 #9kT.6}I@*R=*\R*R@*55q5J5o469#+?kT>}i@ i469#+?kT.}iyn469#+?kT.}i@9 69#+?kT.}i R R4 *R R9 @pϚ?  j`8 4QR1S?jqQ0KS8??@Z jRT#q RTCq@R@ 5)Kq'kK @4K 5*Rk TsO@Rcgk`?֪k@g@c@9{QkQ KJ4O@R`?R8{4#qaTO@R`?R8{CqTO@R`?֡O@R`?R$8R9{ *R_kTO@Rk`?֦k@9ZQkw ?@Khz8 4O@`?9Z@*4*RkTO@R`?֦@9Qk @8O@`?֠K@ #T9 RSA[BcCkDsE*{Ϩ_{ Ҡ#'Q!4CR'@a#@?9 @{Ũ_{S*D@?*D @@s~s D@?֠KkcTSA@{è_ _ ; *_ 'c.@A {i*HRRrBRcqaT{$5*_ ՠ8<@aX"@ 4X @_Xt g_ր8<@__֠84` X\ RA X R X X @RX" BRX* A X @bR * X @bR * X @ BR* wX; `  9zՠ8@T9ՁXXCX8!H!@X @!t!*4X X!XT X X @ՠX_@`( ((`($`($dp0@"(#("(@"(BB|SB_qTB|SB_q`T_q`TXX_ _4!X@ X@ X @RX" BRX* AX @bR * X @bR * X @ BR* XXT@ՠX`X RAX ? _(,(, ((`($`("(#("((`4X 4Xy X X @   @X  X @ @`X!@( ("(`4XW `4XO X@!777/777?7X_(Power on...      arm trust firmware.    boost spi speed.    setup early c stack.   begin warm reset...    warm reset done.    set PEU split mode.    PEU0 enable linkup.    cfg frequency.     manual cfg freq(0:no, 1:yes) : input cpu freq(default:2200 ) :        input lmu freq(default:400 ) : input fio freq(default:500 ) : input dmm freq(default:1200 ) :        input trace freq(default:200) :        cpu freq :      lmu freq :      fio freq :      dmm freq :      trace freq :     using default freq settings. set peu reverse mode.   peu split mode X8    peu split mode X4_X4   peu split mode X4_X1   begin bist loopback.   I am slave.      peu0 set lane number.   mcu init.      enable timer counter.   enable top half sram.   clean whole sarm.    set flash to non secure access. enable I-cache.     bl2 phase.      set bl2 stack.     wake up second cpu.    disable DFS.     enable peu link negotiation. check peu0 pipe clk status.  check peu1 pipe clk status.  gic init.      begin per core init.   entry bl2 form bl1.    mark 1.       mark 2.       hardwarm reset.     fatalerror reset.    wdt reset.      temperature reset.    %aT$aT@#aT(#aT`"aT !aT aT` aT@aTxaT@aTaT aT XaTaT`aTaT8aT@paTaTaT aT~PaT`zaTvaTraT@n0aTjhaTfaT baT^aT`ZH aTV aTR aT@Nt aT J aT Fl aT B( aT >` aT` :aT 6aT 2TaT@ .aT *aT &aT "@aT xaT` aT aT aT@XaT aTaT uR_`^\ZXVTRPNLJHFDB@|"x"t"p"l"h"d"`"\"X"T"x#r#l#f#`#x$K$p$$h$`$p"-"U"X$x4l4x5~6l6Z6xVlfbw1w`X!X !X !X !X !X !X !X !X ,X X X X X X X X |SX |S!X |SX _((( ((((( ($(((,(0(4(8(<(@(D(H("-B|SB_qTtaT_`,X+B|SB_qT+X*B|SB _qAT+X @x )*X @* a*X#@cqTb(B|SB _qAT(X @x b'(X @* &B|SB _qAT&X @x %A'X @* *$B|SB c*B$B|SB c*#B|SB c*c4b#!%X @* "$X @* Ra$X a$X @"X#@cqTbR qATRkAT R"X BB|SB _qT"X "X X#@cq!TB|SB _qT X X B|SB _qT! XX B|SB _qTR_qT#R_q@TCR_ qTcR_qTR_q T_qTAX @p* X#@cqTB|SB _qTR_qT#R_q@TCR_ qTcR_qTR_q T_qTAX @t* TXB|SB _qATX @x X @* AX#@c SqTBB|SB _qATX @x BaX @* *bB|SB c*B|SB c*c4X @* aX @* RX X @ X#@c SqTbR qATRkAT RAX b B|SB _qTX@ X X#@c Sq!TB|SB _qTAX X B|SB _qTR_qT#R_q@TCR_ qTcR_qTR_q T_qTa X @p* X#@c SqTB|SB _qTR_qT#R_q@TCR_ qTcR_qTR_q T_qTaX @t* _ @,,, ,$, ,$, , , ,,@ ,,8,,, , ,$,,,,,,8,*"B|SB_qaT2x"B|SB_qaT2x"B|SB_qaTX TX @X ?_,,B|SB_qTaT_W_XB|SB_qTRX TX aX` AX !X X@ X X X  X ?`R!X RX ?_ ,, ,,,,, ,$,(, , ( B|SB_qaT X`  X X X X X X X X@ X X X X X X X Ta X A X A X A X ! X ! X ! X ! X ! X  X  X  X  X  X  X  X ?_IIII C,C,C,C,C, C,$C,(C, C,C,C,C,C, C,$C,(C, C,C,C,C,C, C,$C,(C, C,C,C,C,C, C,$C,(C,B|SB_qTX yX @2 yX@  yX  yaX  yAX  y!X@  yX  y X  y X @2 y X  ya X  yA X  y! X`  y X  y X y X ywTA X y! X @2 y X@ y X y X y X ya X@ yA X y! X y X @2 y X  y X y X ya X` yA X  y! X y X y?_$ A22,(Ð,,,,Ð,Ð,Ð,Ð,(,,,,,,,,,(à, , , ,à,à,à,à,(,,,,,,,,B|SB_q T"B|SBB_qaTbB|SB _qTR$R_q T#RDR_qTCRdR_ q T_qT!X$!X"@BtB*"X#@cq!TB|SBB_qaTB|SB _qTR$R_q T#RDR_qTCRdR_ q T_qTAX$AX"@BtB*" B|SBB_qaT B|SB _qTR$R_q T#RDR_qTCRdR_ q T_qT X$ X"@BtB*"T" B|SBB_ qaTbB|SB _qTR$R_q T#RDR_qTCRdR_ q T_qTX$X"@BtB*"X#@c Sq!TB|SBB_@qaTB|SB _qTR$R_q T#RDR_qTCRdR_ q T_qTX$X"@BtB*"?_,,,, ,,$,,,, ,AH@" H@7X!"!lSA"!|S! @c2 c  cR R#RcR*_(X(qAT"@B_qTR""@B2""@B_qT "@B2"_(_aX`@8qT(qT(qAT"@B_qTR""@B2""@B_qT "@B2"R(qAT"@B_qTR""@B2""@B_qT "@B2"@R(qAT"@B_qTR""@B2""@B_qT "@B2"_( XR(qAT"@B_qTR""@B2""@B_qT "@B2"R(qAT"@B_qTR""@B2""@B_qT "@B2"cр(Ú @ T$hT<HT(qAT"@B_qTR""@B2""@B_qT "@B2"T_(AXR(qAT"@B_qTR""@B2""@B_qT "@B2"@R(qAT"@B_qTR""@B2""@B_qT "@B2"_(9!L _ATN9z?`_֞T>@T@@P@ @@ B AT DCBA Ȳ@@՟@>1@>>DҀG@!?՟?_֡_____  v1.4(release):d67b0fb-dirtyBuilt : 20:05:06, Jan 6 2020dcu %d : 0x%lx = 0x%08x Initializing PCIe controller 0x%lx startbus %d, devfunc %d p3t7x;|?CG KO S !W!!!"["""#_###"$>":(805<P ;$9+D ` x>":(05 ;$+<D P `x"0"(0<Px(0@<@Px 5" End Training. phyinit201707.bin error , please checkout. Mcu Start Work ... Using 2017.07 Trainig Firmware Mcu Channel %d Dimm_Capacity = %ldGB Begin Adapter alg ... Final Common Cfg Val List: mr1 = 0x%x mr5 = 0x%x mr6 = 0x%x cpuODTImpedance = %d, code = 0x%x cpuTxImpedance = %d, code = 0x%x Could't find proper parameters ! End Adapter alg. MCU Freq:%dMHZ, MCU Capacity:%ldGB DIMM Don't Probed! 2 UMCTL2_REGS_SBRSTAT = 0x%x Channel %d Scrub Mem Fininshed in normal_scrub_mem normal scrube begin. after clr ECCCNT : UMCTL2_REGS_ECCERRCNT = 0x%x after clr MCU_ERR_STA_REG: MCU_ERR_STA_REG = 0x%x after clr correctable error addr 0x84: = 0x%x after clr error addr 0x88: = 0x%x after clr 0x8c: = 0x%x after clr 0x90: = 0x%x after clr 0x94: = 0x%x after clr uncorrectable error addr 0xa4: = 0x%x after clr error addr 0xa8: = 0x%x after clr 0xac: = 0x%x after clr 0xb0: = 0x%x after clr 0xb4: = 0x%x UMCTL2_REGS_MSTR = 0x%x DDR4 SDRAM/ non-DDR4 SDRAM/x4/x8/x16/unsupported data width/1R/2R/no ECC UMCTL2_REGS_MSTR = 0x%x , OFFSET = 0x%x UMCTL2_REGS_STAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_MRCTRL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_MRCTRL1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_MRSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PWRCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PWRTMG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_HWLPCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHCTL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHCTL1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHCTL2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHCTL4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHCTL3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHTMG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RFSHTMG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCCFG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCCFG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCCLR = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCERRCNT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCADDR0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCADDR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCSYN0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCSYN1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCSYN2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCBITMASK0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCBITMASK1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCBITMASK2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCUADDR0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCUADDR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCUSYN0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCUSYN1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCUSYN2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCPOISONADDR0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCPOISONADDR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CRCPARCTL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CRCPARCTL1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CRCPARCTL2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CRCPARSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT5 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT6 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_INIT7 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DIMMCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_RANKCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG5 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG8 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG9 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG10 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG11 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG12 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DRAMTMG15 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ZQCTL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ZQCTL1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFITMG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFITMG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFILPCFG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFILPCFG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFIUPD0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFIUPD1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFIUPD2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFIMISC = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFITMG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFITMG3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFISTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBICTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DFIPHYMSTR = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP5 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP6 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP7 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP8 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP9 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP10 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADDRMAP11 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ODTCFG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ODTMAP = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SCHED = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SCHED1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PERFHPR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PERFLPR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PERFWR1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DQMAP5 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBGCAM = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBGCMD = 0x%x , OFFSET = 0x%x UMCTL2_REGS_DBGSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SWCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SWSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARCFG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARCFG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARCFG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARCFG3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARSTAT0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARSTAT1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARWLOG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARWLOG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARWLOG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARAWLOG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARAWLOG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARRLOG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARRLOG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARARLOG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_OCPARARLOG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_POISONCFG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_POISONSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ADVECCINDEX = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCPOISONPAT0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCPOISONPAT1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_ECCPOISONPAT2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CAPARPOISONCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_CAPARPOISONSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_RFSHCTL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_RFSHTMG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCCFG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGR_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGW_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCTRL_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGQOS0_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGQOS1_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGWQOS0_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGWQOS1_0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SBRCTL = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SBRSTAT = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SBRWDATA0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_INT3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_INT4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_INT6 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_INT7 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG4 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG5 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG8 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG9 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG10 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG11 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG12 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DRAMTMG15 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_ZQCTL0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DFITMG0 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DFITMG1 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DFITMG2 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_DFITMG3 = 0x%x , OFFSET = 0x%x UMCTL2_REGS_SHADOW_ODTCFG = 0x%x , OFFSET = 0x%x UMCTL2_REGS_PCFGW_0 = 0x%x , OFFSET = 0x%x Concurrence Scrub_Mem Init Begin ... Scrub Mem Init Done. ***************TxDqDlyTg0********************** slice_num = %d bit_num = %d, TxDq%dDlyTg0 addr = %x, value = 0x%x ***************TxDqsDlyTg0********************** CDD_RR_3_2 = 0x%x CDD_RR_3_1 = 0x%x CDD_RR_3_0 = 0x%x CDD_RR_2_3 = 0x%x CDD_RR_2_1 = 0x%x CDD_RR_2_0 = 0x%x CDD_RR_1_3 = 0x%x CDD_RR_1_2 = 0x%x CDD_RR_1_0 = 0x%x CDD_RR_0_3 = 0x%x CDD_RR_0_2 = 0x%x CDD_RR_0_1 = 0x%x CDD_WW_3_2 = 0x%x CDD_WW_3_1 = 0x%x CDD_WW_3_0 = 0x%x CDD_WW_2_3 = 0x%x CDD_WW_2_1 = 0x%x CDD_WW_2_0 = 0x%x CDD_WW_1_3 = 0x%x CDD_WW_1_2 = 0x%x CDD_WW_1_0 = 0x%x CDD_WW_0_3 = 0x%x CDD_WW_0_2 = 0x%x CDD_WW_0_1 = 0x%x CDD_RW_3_3 = 0x%x CDD_RW_3_2 = 0x%x CDD_RW_3_1 = 0x%x CDD_RW_3_0 = 0x%x CDD_RW_2_3 = 0x%x CDD_RW_2_2 = 0x%x CDD_RW_2_1 = 0x%x CDD_RW_2_0 = 0x%x CDD_RW_1_3 = 0x%x CDD_RW_1_2 = 0x%x CDD_RW_1_1 = 0x%x CDD_RW_1_0 = 0x%x CDD_RW_0_3 = 0x%x CDD_RW_0_2 = 0x%x CDD_RW_0_1 = 0x%x CDD_RW_0_0 = 0x%x    PPQRQRSSTimed out waiting for bus Read Spd Begin... Parse SPD Data ... Error! spd byte42 = 0 Error! spd byte43 = 0 DDR frequency config... DDR frequence: %d RDIMM UDIMM SODIMM LRDIMM/%d Bank Groups/%d Banks/Cloumn 9/Column 10/Column 11/Column 12/Row 12/Row 13/Row 14/Row 15/Row 16/Row 17/Row 18/X4/X8/X16/X32/1 Rank/2 Rank/3 Rank/4 Rank/5 Rank/6 Rank/7 Rank/8 Rank/NO ECC/ECC/Standard /Mirror Module:Samsung Module:Micron Module:Hynix Module:KingSton Module:Ramaxel Module:Unknown/Dram:Samsung/Dram:Micron/Dram:Hynix/Dram:KingSton/Dram:Ramaxel/Dram:Unknown/Serial:0x%x tRCDmin = %dps tRPmin = %dps tRASmin = %dps tRCmin = %dps tFAWmin = %dps tRRD_Smin = %dps tRRD_Lmin = %dps tCCD_Lmin = %dps tWRmin = %dps tWTR_Smin = %dps tWTR_Lmin = %dps 0x%x 1D Training Begin ... Training Success Training Failed End of initialization End of fine write leveling End of read enable training End of read delay center optimization End of write delay center optimization End of 2D read delay/voltage center optimization End of 2D write delay/voltage center optimization End of max read latency training End of read dq deskew training End of LCDL offset calibrtion End of LRDIMM Specific training End of CA training End of MPR read delay center optimization End of Write leveling coarse delay read no message 2D Training Begin ... > ;":$9(8+05<D P ` x> ;":$(+05<D P `x       $04d@pDtP`T    (08wr2pre = 0x%x tFAWmin = 0x%x tRASmax = 0x%x tRASmin = 0x%x tXP = 0x%x rd2pre = 0x%x tRCmin = 0x%x write_latency = 0x%x read_latency = 0x%x rd2wr = 0x%x wr2rd = 0x%x tRCDmin = 0x%x tCCD_Lmin = 0x%x tRRD_Lmin = 0x%x tRPmin = 0x%x tCCD_S = 0x%x tRRD_Smin = 0x%x wr2rd_s = 0x%x <Pp9` -M__ P_#eGTQ#u:aY<T(Q?  !9!!!7"U"j""""#_####$g$$$$.%h%%4&S&r&&&&&:'p''''(Q((()3)b))))*Y*****+b++++,0,G,h,,,,,,,,,-;-R------.C.k..... //F/\/////#0g000:1111 252h222373l333 4@4e4445B5r55h252573(6 4Y66667`7777858Z88889M999 :&:?:o:::+;Y;;;<\<<<=I={===>>4>U>v>>>>>?? EyeCenter) Units=1/32 UI PMU4: DB %d Lane %d: %3d %3d -> %3d PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED) PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED) PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d PMU4: DB %d Lane %d: (DISCONNECTED) PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge PMU3: WrDq DM byte%2d with Errcnt %d PMU3: WrDq DM byte%2d avgDly 0x%04x PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d) PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d PMU3: Precharge all open banks PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter) PMU4: MRW Passing Regions (coarseVal, fineLeft fineRight -> fineCenter) PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the smaller delay PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d) PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d PMU1: Start MRD/nMWD %d for csn %d PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED) PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED) PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter) PMU4: DB %d nibble %d: (DISCONNECTED) PMU4: DB %d nibble %d: %3d %3d -> %3d PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d) PMU2: incPdbDly: lg %d nib %d dimm %d val %d addr 0x%08x : %d -> %d PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d PMU: Error: Read deskew training has been requested, but csrMajorModeDbyte[2] is set PMU0: goodbar = %d for RDWR_BLEN %d PMU3: db%d l%d saw %d issues at rxClkDly %d PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d PMU3: lane %d PBD = %d PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d PMU2: db%d l%d already passed rxPBD = %d PMU0: db%d l%d, PBD = %d PMU: Error: dbyte %d lane %d failed read deskew PMU1: AcsmCsMapCtrl%02d 0x%04x PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Type PMU: Error: Both 2t timing mode and ddr4 geardown mode specifed in the messageblock's PhyCfg and MR3 fields. Only one can be enabled PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d PMU10: CSA=0x%02X, CSB=0x%02X, TSTAGES=0x%04X, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3 PMU10: CSA=0x%02X, CSB=0x%02X, TSTAGES=0x%04X, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4 PMU10: CS=0x%02X, TSTAGES=0x%04X, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType=%d PMU10: Pstate%d MR0=0x%04X MR1=0x%04X MR2=0x%04X PMU10: Pstate%d MRS MR0=0x%04X MR1=0x%04X MR2=0x%04X MR3=0x%04X MR4=0x%04X MR5=0x%04X MR6=0x%04X PMU10: Pstate%d MRS MR1_A0=0x%04X MR2_A0=0x%04X MR3_A0=0x%04X MR11_A0=0x%04X PMU10: Pstate%d MRS MR1_A0=0x%04X MR2_A0=0x%04X MR3_A0=0x%04X MR4_A0=0x%04X PMU1: AcsmOdtCtrl%02d 0x%02x PMU1: HwtCAMode set PMU3: DDR4 infinite preamble enter/exit mode %d PMU1: In rxenb_train() csn=%d pstate=%d PMU3: Finding DQS falling edge PMU3: Searching for DDR3/LPDDR3/LPDDR4 read preamble PMU3: dtsm fails Even Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x PMU3: dtsm fails Odd Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x PMU3: Preamble search pass=%d anyfail=%d PMU: Error: RxEn training preamble not found PMU3: Found DQS pre-amble PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training PMU3: RxEn aligning to first rising edge of burst PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads PMU3: MREP Delay = %d PMU3: Errcnt for MREP nib %2d delay = %2d is %d PMU3: MREP nibble %d sampled a 1 at data buffer delay %d PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d PMU2: MREP did not find a 0 to 1 transition for all nibbles. Assuming 0 delay was already in the passing region for failing nibbles PMU3: Training DIMM %d CSn %d PMU3: exitCAtrain_lp3 cs 0x%x PMU3: enterCAtrain_lp3 cs 0x%x PMU3: CAtrain_switchmsb_lp3 cs 0x%x PMU3: CATrain_rdwr_lp3 looking for pattern %x PMU3: exitCAtrain_lp4 PMU3: DEBUG set_lp4xcavref 1: idx = %d, vref = %d, cs = %d PMU3: DEBUG set_lp4xcavref 2: memclkdly_cal = %d %x PMU3: DEBUG set_lp4xcavref 2: memclkdly_act = %d %x PMU3: DEBUG set_lp4xcavref 2 waitingPMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x PMU3: DEBUG enterCAtrain_lp4 2 PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode PMU3: DEBUG enterCAtrain_lp4 5: Send MR13 to turn on CA training PMU3: DEBUG enterCAtrain_lp4 6: idx = %d vref = %x mr12 = %x PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x PMU1: DEBUG enterCAtrain_lp4 10 PMU3: CATrain_rdwr_lp4 looking for pattern %x PMU3: Phase %d CAreadbackA db:%d %x xo:%x PMU3: Phase %d CAreadbackB db:%d %x xo:%x PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%% PMU3: DEBUG lp4SetCatrVref 2 PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d PMU3: DEBUG lp4SetCatrVref 4: mr12= %x send vref= %x to db=%d PMU3: DEBUG lp4SetCatrVref 5 PMU10:Optimizing vref PMU4:mr12:%2x cs:%d chan %d r:%4x PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d Failed to find sufficient CA Vref Passing Region for CS %d channel %d PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d PMU3:Calculated %d for AtxImpedence from acx %d. PMU3:CA Odt impedence ==0. Use default vref. PMU3:Calculated %d.%d%% for Vref MR12=0x%x. PMU3: CAtrain_lp PMU3: CAtrain Begins. PMU3: CAtrain_lp testing dly %d PMU5: CA bitmap dump for cs %x PMU5: CAA%d %02xPMU5: CAB%d PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d PMU3:Raw CA setting :%x PMU3:ATxDly setting:%x margin:%d PMU3:InvClk ATxDly setting:%x margin:%d PMU3:No Range found! PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d PMU3: no neg clock => CA setting anib=%d, :%d PMU3:Normal margin:%d PMU3:Inverted margin:%d PMU3:Using Inverted clock PMU3:Using normal clk PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d PMU3: Setting ATxDly for anib %x to %x PMU: Error: CA Training Failed. PMU1: Writing MRs PMU4:Using MR12 values from 1D CA VREF training. PMU3:Writing all MRs to fsp 1 PMU10:Lp4Quickboot mode. PMU3: Writing MRs PMU10: Setting boot clock divider to %d PMU3: Resetting DRAM PMU3: setup for RCD initalization PMU3: pmu_exit_SR from dev_init() PMU3: initializing RCD PMU10: **** Executing 2D Image **** PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x **** PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x **** PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x **** PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x **** PMU10: **** Start LPDDR4X Training. PMU Firmware Revision 0x%04x **** PMU: Error: Mismatched internal revision between DCCM and ICCM images PMU10: **** Testchip %d Specific Firmware **** PMU1: LRDIMM with EncodedCS mode, one DIMM PMU1: LRDIMM with EncodedCS mode, two DIMMs PMU1: RDIMM with EncodedCS mode, one DIMM PMU2: Starting LRDIMM MREP training for all ranks PMU199: LRDIMM MREP training for all ranks completed PMU2: Starting LRDIMM DWL training for all ranks PMU199: LRDIMM DWL training for all ranks completed PMU2: Starting LRDIMM MRD training for all ranks PMU199: LRDIMM MRD training for all ranks completed PMU2: Starting RXEN training for all ranks PMU2: Starting write leveling fine delay training for all ranks PMU2: Starting LRDIMM MWD training for all ranks PMU199: LRDIMM MWD training for all ranks completed PMU2: Starting read deskew training PMU2: Starting SI friendly 1d RdDqs training for all ranks PMU2: Starting write leveling coarse delay training for all ranks PMU2: Starting 1d WrDq training for all ranks PMU2: Running DQS2DQ Oscillator for all ranks PMU2: Starting 1d RdDqs training for all ranks PMU2: Starting MaxRdLat training PMU2: Redoing LRDIMM MREP training for all ranks PMU2: Redoing LRDIMM DWL training for all ranks PMU2: Redoing LRDIMM MRD training for all ranks PMU2: Redoing LRDIMM MWD training for all ranks PMU2: Starting 2d RdDqs training for all ranks PMU2: Starting 2d WrDq training for all ranks PMU3:read_fifo %x %x PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block. PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block. PMU: Error: Invalid BPZNResVal of 0x%x specified in message block. PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x PMU3: fixRxEnBackOff dly:%x PMU3: Entering setupPpt PMU3: Start lp4PopulateHighLowBytes PMU3:Dbyte Detect: db%d received %x PMU3:getDqs2Dq read %x from dbyte %d PMU3:getDqs2Dq(2) read %x from dbyte %d PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to PMU4: Dbyte %d dqs2dq = %d/32 UI PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x PMU3: Performing DDR4 geardown sync sequence PMU1: Enter self refresh PMU1: Exit self refresh PMU1: DDR4 update 2nCk WPre Setting disable %d PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x) PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 -- PMU5: [%d]:0x %4x %4x %4x %4x %4x %4x %4x %4x %4x %4x PMU2: dump delays - pstate=%d dimm=%d csn=%d PMU3: Printing Mid-Training Delay Information PMU5: CS%d <> 0 TrainingCntr <> coarse(15:10) fine(9:0) PMU5: CS%d <> 0 RxEnDly, 1 RxClkDly <> coarse(10:6) fine(5:0) PMU5: CS%d <> 0 TxDqsDly, 1 TxDqDly <> coarse(9:6) fine(5:0) PMU5: CS%d <> 0 RxPBDly <> 1 Delay Unit ~= 7ps PMU5: all CS <> 0 DFIMRL <> Units = DFI clocks PMU1: Set DMD in MR13 and wrDBI in MR3 for training PMU: Error: getMaxRxen() failed to find largest rxen nibble delay PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d PMU1: skipping CDD calculation in 2D image PMU3: Calculating CDDs for pstate %d PMU3: rxDly[%d][%d] = %d PMU3: txDly[%d][%d] = %d PMU3: allFine CDD_RR_%d_%d = %d PMU3: allFine CDD_WW_%d_%d = %d PMU3: CDD_RR_%d_%d = %d PMU3: CDD_WW_%d_%d = %d PMU3: allFine CDD_RW_%d_%d = %d PMU3: allFine CDD_WR_%d_%d = %d PMU3: CDD_RW_%d_%d = %d PMU3: CDD_WR_%d_%d = %d PMU3: F%dBC2x_B%d_D%d = 0x%02x PMU3: F%dBC3x_B%d_D%d = 0x%02x PMU3: F%dBC4x_B%d_D%d = 0x%02x PMU3: F%dBC5x_B%d_D%d = 0x%02x PMU3: F%dBC8x_B%d_D%d = 0x%02x PMU3: F%dBC9x_B%d_D%d = 0x%02x PMU3: F%dBCAx_B%d_D%d = 0x%02x PMU3: F%dBCBx_B%d_D%d = 0x%02x PMU1: enter_lp3: DEBUG: pstate = %d PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d PMU1: enter_lp3: DEBUG: pllbypass = %d PMU1: enter_lp3: DEBUG: forcecal = %d PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x PMU1: enter_lp3: DEBUG: dacval_out = 0x%x PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x PMU3: Loading DRAM with BIOS supplied MR values and entering self refresh prior to exiting PMU code. PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d PMU4: Setting RCW FxRC%Xx = 0x%02x PMU4: Setting RCW FxRC%02X = 0x%02x PMU1: DDR4 update Rd Pre Setting disable %d PMU2: Setting BCW FxBC%Xx = 0x%02x PMU2: Setting BCW BC%02X = 0x%02x PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x PMU2: Setting BCW PBA mode BC%02X = 0x%02x PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x PMU4: DB %d, value 0x%02x PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine %2d PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F PMU3: Disable parity in F0RC0E PMU3: Writing D4 Data buffer Control words BC00 -> BC0E PMU1: setAltCL Sending MR0 0x%x cl=%d PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d PMU2: Setting D3R RC%d = 0x%01x PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11 PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers. Please see the pub databook PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. Please see the pub databook PMU0: PHY VREF @ (%d/1000) VDDQ PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x PMU0: initalizing global vref to %d range %d PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d PMU3: Fine write leveling hardware search increasing TxDqsDly until full bursts are seen PMU3: Exiting write leveling mode PMU3: got %d for cl in load_wrlvl_acsm PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d PMU3: left eye edge search db:%d ln:%d dly:0x%x PMU3: right eye edge search db:%d ln:%d dly:0x%x PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x) PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy PMU: Error: Failed write leveling coarse PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x PMU3: DWL delay = %d PMU3: Errcnt for DWL nib %2d delay = %2d is %d PMU3: DWL nibble %d sampled a 1 at delay %d PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d PMU2: DWL did nto find a rising edge of memclk for all nibbles. Failing nibbles assumed to have rising edge at fine delay 63 PMU: Error:Mailbox Buffer Overflowed. PMU: ***** Assertion Error - terminating ***** PMU1: swapByte db %d by %d PMU3: get_cmd_dly max(%d ps, %d memclk) = %d PMU0: Write CSR 0x%06x 0x%04x PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d PMU: Error: acsm_set_cmd to non existant instruction adddress %d PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x PMU1: acsm_addr %02x, acsm_flgs %04x, ddr_cmd %02x, cmd_dly %02x, ddr_addr %04x, ddr_bnk %02x, ddr_cs %02x, cmd_rcnt %02x, AcsmSeq0/1/2/3 %04x %04x %04x %04x PMU: Error: Polling on ACSM done failed to complete in acsm_poll_done()... PMU1: acsm RUN PMU1: acsm STOPPED PMU1: acsm_init: acsm_mode %04x mxrdlat %04x PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d PMU1: setAcsmCLCWL: CASL %04d WCASL %04d PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x PMU3: Written MRS to CS=0x%02x PMU3: Entering Boot Freq Mode. PMU: Error: Boot clock divider setting of %d is too small PMU3: Exiting Boot Freq Mode. PMU3: Writing MR%d OP=%x PMU: Error: Delay too large in slomo PMU3: Enable Channel A PMU3: Enable Channel B PMU3: Enable All Channels PMU2: Use PDA mode to set MR%d with value 0x%02x PMU3: Written Vref with PDA to CS=0x%02x PMU1: start_cal: DEBUG: setting CalRun to 1 PMU1: start_cal: DEBUG: setting CalRun to 0 PMU1: lock_pll_dll: DEBUG: pstate = %d PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d PMU1: lock_pll_dll: DEBUG: pllbypass = %d PMU3: SaveLcdlSeed: Saving seed seed %d PMU1: in phy_defaults() PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d cd>dwdddd e+eieeeeef#fEfdffff]ggg h:hqhhhiKi{iKi{iKihiii*jNjjjkfkkkkkl/l^llllm)mTmmmmn#nBn_nnnoyoop#p^ppp qeqqq>rhrrr8sassss%t{tttt{tu:u{tuuuvpvvwCwXwww;xxxttxyhEyyyyyyzFzmz<Pp9` -M__ P_#eGTQ#u:aY<T(Q?  !9!!!7"U"j""""#_####$g$$$$.%h%%4&S&r&&&&&:'p''''(Q((()3)b))))*Y*****+b++++,0,G,h,,,,,,,,,-;-R------.C.k..... //F/\/////#0g000:1111 252h222373l333 4@4e4445B5r55h252573(6 4Y66667`7777858Z88889M999 :&:?:o:::+;Y;;;<\<<<=I={===>>4>U>v>>>>>?? MR[6:0] 0x%02x PMU0: Converting MR 0x%04x to vrefIdx PMU0: DAC %d Range %d PMU0: Range %d, Range_idx %d, vref_idx offset %d PMU0: MR 0x%04x -> VrefIdx %d PMU: Error: Illegal timing group number ,%d, in getPtrVrefDq PMU1: VrefDqR%dNib%d = %d PMU0: VrefDqR%dNib%d = %d PMU0: ----------------MARGINS------- PMU0: R%d_RxClkDly_Margin = %d PMU0: R%d_VrefDac_Margin = %d PMU0: R%d_TxDqDly_Margin = %d PMU0: R%d_DeviceVref_Margin = %d PMU0: ----------------------- PMU0: eye %d's for all TG's is [%d ... %d] PMU0: ------- FFEmeasurements ----- PMU0: FFE_weight %d @ drvStren %d PMU4: %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d >%3d< %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d PMU4: -- DB%d L%d -- centers: delay = %d, voltage = %d PMU5: <> 0 TxDqDlyTg%d <> coarse(6:6) fine(5:0) PMU5: <> 0 messageBlock VrefDqR%d <> MR6(6:0) PMU5: <> 0 RxClkDlyTg%d <> fine(5:0) PMU5: <> 0 VrefDAC0, 1 VrefDAC1 <> DAC(6:0) PMU0: tgToCsn: tg %d + 0x%04x -> csn %d PMU: Error: LP4 rank %d cannot be mapped on tg %d PMU3: Sending vref %d, Mr = 0X%05x, to all devices PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x -------- PMU0: training lanes 0x%03x using lanes 0x%03x PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x ------- PMU4: Delay Stepsize = %d Fine, Voltage Stepsize = %d DAC PMU4: Delay Weight = %d, Voltage Weight = %d PMU0: raw 0x%x allFine %d incDec %dPMU0: db%d l%d, voltage 0x%x (u_r %d) delay 0x%x (u_r %d) - lcdl %d mask 0x%x PMU0: DB%d L%d, Eye %d, Seed = (0x%x, 0x%x) PMU3: 2D Enables : %d, 1, %d PMU3: 2D Delay Ranges: OOPL[0x%04x,0x%04x], IP[0x%04x,0x%04x], OOPR[0x%04x,0x%04x] PMU3: 2D Voltages : %d %d DEBUG: min %d, max %d PMU0: seed 0 = (%d,%d) (center) PMU0: seed 1 = (%d,%d). edge at idx %d PMU0: seed 2 = (%d,%d) edge at idx %d PMU0: Search point %d = (%d,%d) PMU0: YMARGIN: ^ %d, - %d, v %d. rate %d = %d PMU0: XMARGIN: center %d, edge %d. = %d PMU0: ----------- weighting (%d,%d) ---------------- PMU0: X margin - L %d R %d - Min %d PMU0: Y margin - L %d R %d - Min %d PMU0: center (%d,%d) weight = %d PMU0: ---- updating search point %d ----- PMU3: Looking for %d (center,left,right) local maximum PMU1: ##### (%d to go) starting (%d, %d) ##### PMU1: local_max is 0, stop searching. PMU0: picking left (%d == %d) PMU0: picking right (%d == %d) PMU0: picking down (%d == %d) PMU0: picking up (%d == %d) PMU1: local_max is center, stop searching. PMU3: center (%3d, %3d) moving (%2i, %2i) -- L %d, R %d, C %d, U %d, D %d PMU0: max iterations (%d) reached. Final center (%d,%d), weight %d PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions PMU3: Optimal allFine Center (%d,%d), found in %d (center,left,right) region, with weight %d. PMU0: merging lanes=%d..%d, centerMerge_t %d PMU0: laneVal %d is disable PMU0: checking common center %d against current center %d PMU: Error: getCompoundEye Called on lane%d eye with non-compatible (%d delay, %d voltage) centers. %d != %d PMU0: laneItr %d is disable PMU0: lane %d, data_idx %d, offset_idx %d, = [%d..%d] PMU0: lane %d, data_idx %d, offset_idx %d, offset_idx out of range! PMU0: mergeData[%d] = max_v_low %d, min_v_high %d PMU1: writing merged center (%d,%d) back to dataBlock[%d]. doDelay %d, doVoltage %d PMU0: applying relative (%i,%i) back to dataBlock[%d]. doDelay %d, doVoltage %d PMU0: drvstren %x is idx %d in the table PMU4: truncating FFE drive strength search range. Out of drive strengths to check. PMU5: Weak 1 changed to pull-up %5d ohms, pull-down %5d ohms PMU5: Weak 0 changed to pull-up %5d ohms, pull-down %5d ohms PMU0: dlyMargin L %02d R %02d, min %02d PMU0: vrefMargin T %02d B %02d, min %02d PMU3: new minimum VrefMargin (%d < %d) recorded PMU3: new minimum DlyMargin (%d < %d) recorded PMU0: RX finding the per-nibble, per-tg rxClkDly values PMU3: Merging collected eyes [%d..%d) and analyzing for nibble %d's optimal rxClkDly PMU0: dumping optimized eye PMU0: TX optimizing txDqDelays PMU3: Analyzing collected eye %d for a lane's optimal TxDqDly PMU0: eye-lane %d is disable PMU0: TX optimizing device voltages PMU3: Merging collected eyes [%d..%d) and analyzing for optimal device txVref PMU4: VrefDac (compound all TG) Bottom Top -> Center PMU4: DB%d L%d %3d %3d -> %3d (DISCONNECTED) PMU4: DB%d L%d %3d %3d -> %3d PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] (DISCONNECTED) PMU: Error: Dbyte %d nibble %d's optimal rxClkDly of 0x%x is out of bounds PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] PMU0: tx voltage for tg%2d nib%2d to %3d (%d) from eye[%02d] PMU0: vref Sum = %d PMU0: tx voltage total is %d/%d -> %d -> %d PMU0: writing txDqDelay for tg%1d db%1d ln%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] (DISCONNECTED) PMU: Error: Dbyte %d lane %d's optimal txDqDly of 0x%x is out of bounds PMU0: writing txDqDelay for tg%1d db%1d l%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] PMU0: %d (0=tx, 1=rx) TgMask for this simulation: %x PMU0: eye-byte %d is disable PMU0: eye %d weight %d allTgWeight %d PMU5: FFE figure of merit improved from %d to %d PMU4: Adjusting vrefDac0 for just 1->x transitions PMU4: Adjusting vrefDac1 for just 0->x transitions PMU5: Strong 1, pull-up %d ohms PMU5: Strong 0, pull-down %d ohms PMU4: Enabling weak drive strengths (FFE) PMU5: Changing all weak driver strengths PMU5: Finalizing weak drive strengths PMU4: retraining with optimal drive strength settings H||wFailed to obtain reference to image id=%u (%i) Failed to access image id=%u (%i) Firmware Image Package header check failed. Failed to open FIP (%i) fip_file_read: failed to seek Failed to read payload (%i) fip_file_open : Only one open file at a time. Failed to open Firmware Image Package (%i) fip_file_open: failed to seek Failed to read FIP (%i) twywxxwwA flash device is already active. Close first. l}d}~}}}}}| _ M">MDÝ? GmLF)P˽ZSG+P Kz>8Ѕ"((}"(8}<"(X}<"(h}<"(~<K44cpu freq = %dMHz Chip ID :%c_Core number: 64 g9rMugJBooting Trusted Firmware for ft2000plus BL1: %s Failed to load BL2 firmware. BL1: Booting BL2 BL1-FWU: *******FWU Process Started******* BL1: Booting BL31 Unimplemented BL1 SMC Call: 0x%x Nothing to allocate, requested size is zero Failed to determine the size of the image id=%u (%i) Failed to load image id=%u (%i) Image id=%u loaded at address %p, size = 0x%zx h5'jI0xERROR: NOTICE: WARNING: INFO: VERBOSE: !+5? F3666666666H  Tgin0123456789abcdefghijklmnopqrstuvwxyz(fmt null) (null)PANIC at PC : 0xfpL} ]d@=D`$ҽҝD{R>Z_aTW ]d@=D`$ҽҝ     "(X